A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array-Reference-Cited by-同舟云学术

A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Pekny Ted¹,Vu Luyen¹,Tsai Jeff¹,Srinivasan Dheeraj¹,Yu Erwin¹,Pabustan Jonathan¹,Xu Joe¹,Deshmukh Srinivas¹,Chan Kim-Fung¹,Piccardi Michael¹,Xu Kevin¹,Wang Guan¹,Shakeri Kaveh¹,Patel Vipul¹,Iwasaki Tomoko¹,Wang Tongji¹,Musunuri Padma¹,Gu Carl¹,Mohammadzadeh Ali¹,Ghalam Ali¹,Moschiano Violante²,Vali Tommaso²,Park Jaekwan¹,Lee June¹,Ghodsi Ramin¹

Affiliation:

1. Micron Technology,San Jose,CA

2. Micron Technology,Avezzano,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731691.pdf?arnumber=9731691

Reference6 articles.

1. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture

2. 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-line-layer Technology;higuchi;ISSCC,2020

3. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique

4. 30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

5. A floating gate based 3D NAND technology with CMOS under array

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