30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture-Reference-Cited by-同舟云学术

30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Park Jae-Woo,Kim Doogon,Ok Sunghwa,Park Jaebeom,Kwon Taeheui,Lee Hyunsoo,Lim Sungmook,Jung Sun-Young,Choi Hyeongjin,Kang Taikyu,Park Gwan,Yang Chul-Woo,Choi Jeong-Gil,Ko Gwihan,Shin Jaehyeon,Yang Ingon,Nam Junghoon,Sohn Hyeokchan,Hong Seok-In,Jeong Yohan,Choi Sung-Wook,Choi Changwoon,Shin Hyun-Soo,Lim Junyoun,Youn Dongkyu,Nam Sanghyuk,Lee Juyeab,Ahn Myungkyu,Lee Hoseok,Lee Seungpil,Park Jongmin,Gwon Kichang,Jeong Woopyo,Choi Jungdal,Kim Jinkook,Jin Kyo-Won

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365809.pdf?arnumber=9365809

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