High-Density 3-D NAND Cell Array Design With Hybrid Bonding-Reference-Cited by-同舟云学术

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High-Density 3-D NAND Cell Array Design With Hybrid Bonding

Published:2023-11 Issue:11 Volume:70 Page:5638-5644
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Lee Seungmin¹^ORCID,Lim Joonsung¹,Kim Jun Hyoung²,Cho Sunghwan³^ORCID,Lee Yong Kyu⁴,Choi Byoungdeog⁵^ORCID

Affiliation:

1. Flash Process Architecture Team, Samsung Electronics Company, Hwaseong, South Korea

2. Flash Product and Technology, Samsung Electronics Company, Hwaseong, South Korea

3. Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South Korea

4. Samsung Institute of Technology, Samsung Electronics Company, Yongin, South Korea

5. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10294316/10250924.pdf?arnumber=10250924

Reference24 articles.

1. A new cell-type string select transistor in NAND flash memories for under 20 nm node;lee;Proc 4th IEEE Int Memory Workshop,2012

2. All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash

3. Review of Semiconductor Flash Memory Devices for Material and Process Issues

4. Comparison of current 3D NAND chip & cell architecture;choe,0

5. A 1Tb 3b/cell 8th-generation 3D-NAND flash memory with 164 MB/s write throughput and a 2.4 Gb/s interface;kim,0

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