A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices-Reference-Cited by-同舟云学术

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Wu Ping-Chun¹,Su Jian-Wei¹,Hong Li-Yang¹,Ren Jin-Sheng¹,Chien Chih-Han¹,Chen Ho-Yu¹,Ke Chao-En¹,Hsiao Hsu-Ming²,Li Sih-Han²,Sheu Shyh-Shyuan²,Lo Wei-Chung²,Chang Shih-Chieh²,Lo Chung-Chuan¹,Liu Ren-Shuo¹,Hsieh Chih-Cheng¹,Tang Kea-Tiong¹,Chang Meng-Fan¹

Affiliation:

1. National Tsing Hua University,Hsinchu,Taiwan

2. Industrial Technology Research Institute,Hsinchu,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067527.pdf?arnumber=10067527

Reference6 articles.

1. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-Al Devices;wu;ISSCC,2022

2. 9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

3. A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

4. A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

5. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

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1. Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06

2. A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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4. A reconfigurable in‐memory‐computation architecture with in‐situ update and shift capability;Electronics Letters;2024-04

5. 34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18