16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips-Reference-Cited by-同舟云学术

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Su Jian-Wei,Chou Yen-Chi,Liu Ruhui,Liu Ta-Wei,Lu Pei-Jung,Wu Ping-Chun,Chung Yen-Lin,Hung Li-Yang,Ren Jin-Sheng,Pan Tianlong,Li Sih-Han,Chang Shih-Chieh,Sheu Shyh-Shyuan,Lo Wei-Chung,Wu Chih-I,Si Xin,Lo Chung-Chuan,Liu Ren-Shuo,Hsieh Chih-Cheng,Tang Kea-Tiong,Chang Meng-Fan

Funder

Nova

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365984.pdf?arnumber=9365984

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1. ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory;IEEE Transactions on Computers;2024-09

2. FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm² Analog Compute-in-Memory Macro;IEEE Journal of Solid-State Circuits;2024-09

3. An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices;Microelectronics Journal;2024-09

4. Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation;IEEE Journal of Solid-State Circuits;2024-08

5. A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

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