Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture-Reference-Cited by-同舟云学术

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Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture

Published:2024-06 Issue:6 Volume:71 Page:3181-3185
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chen Xi¹,Zhao Yitong¹^ORCID,Guo An¹,Chen Jinwu¹^ORCID,Dong Fangyuan¹,Zhang Zhaoyang¹,Xiong Tianzhu¹,Wang Bo¹^ORCID,Kong Yuyao¹,Si Xin¹^ORCID

Affiliation:

1. National ASIC Center, Southeast University, Nanjing, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Key Research and Development Program of Jiangsu Province

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10561573/10400856.pdf?arnumber=10400856

Reference20 articles.

1. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

2. A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

3. 24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

4. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

5. A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

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