A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations-Reference-Cited by-同舟云学术

A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Fujiwara Hidehiro¹,Mori Haruki¹,Zhao Wei-Chang¹,Chuang Mei-Chen¹,Naous Rawan²,Chuang Chao-Kai¹,Hashizume Takeshi³,Sun Dar¹,Lee Chia-Fu¹,Akarvardar Kerem²,Adham Saman⁴,Chou Tan-Li¹,Sinangil Mahmut Ersin²,Wang Yih¹,Chih Yu-Der¹,Chen Yen-Huei¹,Liao Hung-Jen¹,Chang Tsung-Yung Jonathan¹

Affiliation:

1. TSMC,Hsinchu,Taiwan

2. TSMC,San Jose,CA

3. TSMC,Yokohama,Japan

4. TSMC,Austin,TX

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731754.pdf?arnumber=9731754

Reference6 articles.

1. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021

2. PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

3. A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC;park;ISSCC,2021

4. 24.4 A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

5. 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

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