A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs-Reference-Cited by-同舟云学术

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

Published:2024-09 Issue:9 Volume:59 Page:3032-3044
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Guo An¹,Xi Chen¹,Dong Fangyuan¹,Pu Xingyu¹,Li Dongqi¹,Zhang Jingmin¹,Dong Xueshan¹,Gao Hui¹^ORCID,Zhang Yiran¹,Wang Bo¹^ORCID,Yang Jun¹^ORCID,Si Xin¹^ORCID

Affiliation:

1. School of Integrated Circuits, Southeast University, Nanjing, China

Funder

National Science and Technology Major Project

National Natural Science Foundation of China

Key Research and Development Program of Jiangsu Province

Postgraduate Research and Practice Innovation Program of Jiangsu Province

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10648889/10477933.pdf?arnumber=10477933

Reference32 articles.

1. A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

2. Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

3. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

4. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

5. A 4 nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM based digital-computing-in-memory macro supporting bit-width flexibility and simultaneous MAC and weight update;Mori