Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips-Reference-Cited by-同舟云学术

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Published:2022-02 Issue:2 Volume:57 Page:609-624
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Su Jian-Wei^ORCID,Si Xin^ORCID,Chou Yen-Chi,Chang Ting-Wei,Huang Wei-Hsing,Tu Yung-Ning,Liu Ruhui^ORCID,Lu Pei-Jung,Liu Ta-Wei,Wang Jing-Hong,Chung Yen-Lin,Ren Jin-Sheng,Chang Fu-Chun,Wu Yuan^ORCID,Jiang Hongwu^ORCID,Huang Shanshi^ORCID,Li Sih-Han^ORCID,Sheu Shyh-Shyuan,Wu Chih-I,Lo Chung-Chuan,Liu Ren-Shuo,Hsieh Chih-Cheng^ORCID,Tang Kea-Tiong^ORCID,Yu Shimeng^ORCID,Chang Meng-Fan^ORCID

Funder

Industrial Technology Research Institute

Taiwan Semiconductor Research Institute

TSMC-Joint Developed Project

MediaTek-Joint Developed Project

Ministry of Science and Technology (MOST)-Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9694622/09535152.pdf?arnumber=9535152

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