A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC-Reference-Cited by-同舟云学术

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A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC

Published:2024-11 Issue: Volume:153 Page:106397
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Lin Zhiting,Yu Runru^ORCID,Huo Da,Zhu Qingchuan,Long Miao,Qin Yongqi,Liu Yanchun,Chen Lintao,Wang Simin,Wang Ting,Xing Yousheng,Wen Zeshi,Liu Yu,Li Xin,Dai Chenghu,Zhao Qiang,Peng Chunyu,Wu Xiulong^ORCID

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Reference34 articles.

1. A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks;Birudu;Microelectronics J,2023

2. Cross-coupled 4T2R multi-logic in-memory computing circuit design;Lin;Microelectronics J,2024

3. An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor;Rajput;Memories - Materials, Devices, Circuits and Systems,2023

4. In-memory transposable multibit multiplication based on diagonal symmetry weight block;Tong;IEEE Trans Very Large Scale Integr VLSI Syst,2023

5. A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications;Xiao;Microelectronics J,2022

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