In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block-Reference-Cited by-同舟云学术

In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block

Published:2023-09 Issue:9 Volume:31 Page:1454-1458
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Tong Zhongzhen¹^ORCID,Zhao Yue²^ORCID,Zhang Jin³^ORCID,Lin Zhiting²^ORCID,Lin Xiaoyang¹^ORCID,Wu Xiulong²^ORCID

Affiliation:

1. School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China

2. School of Integrated Circuits, Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China

3. School of Management Science and Engineering, Anhui University of Finance and Economics, Bengbu, China

Funder

National Natural Science Foundation of China

Joint Funds of the National Natural Science Foundation of China

Key Research and Development Program of Anhui Province

Science Fund for Distinguished Young Scholars of Anhui Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10229811/10122574.pdf?arnumber=10122574

Reference14 articles.

1. 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

2. CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

3. A single-channel voltage-scalable 8-GS/s 8-b > 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS;chen;IEEE J Solid-State Circuits,2022

4. 10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

5. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

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2. A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

3. Configurable in-memory computing architecture based on dual-port SRAM;Microelectronics Journal;2024-05

4. A 28-Nm 9t Sram-Based Cim Macro with Capacitance Weighting Module and Redundant Array-Assisted Adc;2024

5. Symmetry in the Bit-Stream Converter Design;Symmetry;2023-10-31