A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks-Reference-Cited by-同舟云学术

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A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

Published:2023-09 Issue: Volume:139 Page:105867
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Birudu Venu,Yellampalli Siva Sankar,Vaddi Ramesh^ORCID

Funder

SRM University

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference41 articles.

1. SRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks;Mu;IEEE Transactions on Circuits and Systems I: Regular Papers,2022

2. SRAM-based computing-in-memory macro with fully parallel one-step multibit computation;Choi;IEEE Solid-State Circuits Letters,2022

3. A brain-inspired ADC-free SRAM-based in-memory computing macro with high-precision MAC for AI application;Xuan,2022

4. In-memory computation of a machine-learning classifier in a standard 6T SRAM array;Zhang;IEEE J. Solid State Circ.,2017

5. A 28-nm compute SRAM with bit-serial logic/arithmetic operationsfor programmable in-memory vector computing;Wang;IEEE J. Solid State Circ.,2019

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A complementary ternary inverter based on the line tunneling field effect transistors;Microelectronics Journal;2024-03

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