Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices-Reference-Cited by-同舟云学术

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Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Venu Birudu¹,Kadiyam Tirumalarao¹,Penumalli Koteswararao¹,Japa Aditya²,Sambatur Sushma Nirmala³,Gu Chongyan²,Yellampalli Siva Sankar¹,Vaddi Ramesh¹

Affiliation:

1. SRM University-AP,School of Engineering and Sciences,Department of Electronics and Communication Engineering,Amaravati, Guntur,Andhra Pradesh,India,522502

2. Queen’s University Belfast,Centre for Secure Information Technologies (CSIT), ECIT,Belfast,U.K.

3. Global Foundries Engineering Private Limited,Bangalore,Karnataka,India,560045

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558683.pdf?arnumber=10558683

Reference35 articles.

1. CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

2. Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

3. Deep Neural Networks for Acoustic Modeling in Speech Recognition: The Shared Views of Four Research Groups

4. ImageNet classification with deep convolutional neural networks;Krizhevsky

5. The MNIST Database of Handwritten Digits;LeCun,1998

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