3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs
Author:
Affiliation:
1. Cornell Tech, New York, NY, United States
Funder
SRC/DARPA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3665314.3670838
Reference17 articles.
1. Rongmei Chen et al. 2020. 3D-Optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes. In IEEE IEDM.
2. Y. H. Chen et al. 2020. Ultra High Density SoIC with Sub-micron Bond Pitch. In IEEE ECTC.
3. Hidehiro Fujiwara et al. 2022. A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. In IEEE ISSCC.
4. A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM with Various High-Speed and Low-Power Techniques;Kyung-Soo Ha;IEEE Journal of Solid-State Circuits (JSSC),2019
5. Jun-Woo Jang et al. 2021. Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC. In ACM/IEEE ISCA.
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