A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration-Reference-Cited by-同舟云学术

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
language:
Short-container-title:

Author:

Tu Fengbin¹,Wang Yiqi¹,Wu Zihan¹,Liang Ling²,Ding Yufei²,Kim Bongjin²,Liu Leibo¹,Wei Shaojun¹,Xie Yuan²,Yin Shouyi¹

Affiliation:

1. Tsinghua University,Beijing,China

2. University of California,Santa Barbara,CA

Funder

National Key R&D Program

NSFC

Beijing S&T Project

Beijing Innovation Center for Future Chip

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731762.pdf?arnumber=9731762

Reference5 articles.

1. A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

2. An 89TOPS/W and 16.3TOPS/mm2All-Digital SRAM-Based Full-Precision Compute-In-Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021

3. A 40nm 4.81 TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree;park;ISSCC,2021

4. 9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

5. A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating;yue;ISSCC,2021

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