Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking-Reference-Cited by-同舟云学术

Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Derakhshandeh Jaber¹,Beyne Eric¹,Beyer Gerald¹,Capuz Giovanni¹,Cherman Vladimir¹,De Preter Inge¹,Gerets Carine¹,Shafahian Ehsan¹,Kennes Koen¹,Jamieson Geraldine¹,Cochet Tom¹,Webers Tomas¹,Tobback Bert¹,Van der Plas Geert¹,La Tulipe Douglas Charles¹,Phommahaxay Alain¹,Miller Andy¹

Affiliation:

1. IMEC,Leuven,Belgium,3001

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816529.pdf?arnumber=9816529

Reference10 articles.

1. 3D Stacking Using Bump-Less Process for Sub 10?m Pitch Interconnects;derakhshandeh;ECTC,2016

2. 10 and 7 μm Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process

3. Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes

4. Morphology of IMC in the binary systems of Co/Sn and Cu/Sn;nagano;MAM,2017

5. Transition from flip chip solder joint to 3D IC microbump: Its effect on microstructure anisotropy

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