Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency
Author:
Affiliation:
1. IMEC,3001 Leuven,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10301149/10301156/10301169.pdf?arnumber=10301169
Reference18 articles.
1. IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
2. Analyzing crosstalk in the presence of weak bridge defects
3. Testing for Faults in Wiring Networks
4. IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
5. Resistance characterization for weak open defects
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1. Boundary-Scan Technology for Chiplet Test;Journal of The Japan Institute of Electronics Packaging;2024-07-01
2. Test and Repair Improvements for UCIe;2024 IEEE European Test Symposium (ETS);2024-05-20
3. New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405;2024 IEEE European Test Symposium (ETS);2024-05-20
4. IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
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