Influence of High-Temperature Bias Stress on Room-Temperature VT Drift Measurements in SiC Power MOSFETs

Abstract

Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for VT stability.