Comparison of Test Methods for Proper Characterization of VT in SiC MOSFETs

Abstract

A survey of methods for characterizing threshold voltage (VT) drift when applied to commercial SiC DMOSFETs was conducted to explore how results can vary from one test to another. Typical linear-with-log-stress-time VT drift was observed with a rate of increase near 50–60 mV/dec for all methods. However, the magnitude of the drift varied greatly depending on the time delay between stress and measurement. A power law recovery ( ) common to all methods results in much smaller VT drifts when using slower methods, meaning long delays between stress and measurement can lead to tests that are unable to adequately discriminate bad devices from good.