Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Abstract

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.