Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD
-
Published:2023-09-23
Issue:10
Volume:14
Page:1822
-
ISSN:2072-666X
-
Container-title:Micromachines
-
language:en
-
Short-container-title:Micromachines
Author:
Oh Jong Hyeok1, Yu Yun Seop1ORCID
Affiliation:
1. ICT & Robotics Engineering, Semiconductor Convergence Engineering, AISPC Laboratory and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si 17579, Gyenggi-do, Republic of Korea
Abstract
In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.
Funder
Basic Science Research Program through NRF of Korea funded by the Ministry of Education
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference50 articles.
1. Science and Engineering Beyond Moore’s Law;Cavin;Proc. IEEE,2012 2. Device Scaling Limits of Si MOSFETs and Their Application Dependencies;Frank;Proc. IEEE,2001 3. Clavelier, L., Deguet, C., Di Cioccio, L., Augendre, E., Brugere, A., Gueguen, P., Le Tiec, Y., Moriceau, H., Rabarot, M., and Signamarcheix, T. (2010, January 6–8). Engineered Substrates for Future More Moore and More than Moore Integrated Devices. Proceedings of the 2010 International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 4. Grenouillet, L., De Salvo, B., Brunet, L., Coignus, J., Tabone, C., Mazurier, J., Le Royer, C., Grosse, P., Jaud, M.A., and Rivallin, P. (2014, January 6–9). Smart Co-Integration of Light Sensitive Layers with FDSOI Transistors for More than Moore Applications. Proceedings of the 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, CA, USA. 5. FinFET-a Self-Aligned Double-Gate MOSFET Scalable to 20 nm;Hisamoto;IEEE Trans. Electron Devices,2000
|
|