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Test data compression using alternating variable run-length code

  • Published:2011-03 Issue:2 Volume:44 Page:103-110
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Ye Bo,Zhao Qian,Zhou Duo,Wang Xiaohua,Luo Min

Funder

Key Project of the Chinese Ministry of Education

Innovation Program of the Shanghai Municipal Education Commission

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference25 articles.

1. LFSR-reseeding scheme achieving low-power dissipation during test;Lee;IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,2007

2. Low-power scan operation in test compression environment;Czysz;IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,2009

3. Data-independent pattern run-length compression for testing embedded cores in SoCs;Ruan;IEEE Trans. Comput.,2007

4. Test data compression for system-on-a-chip using extended frequency-directed run-length code;EI-Maleh;IET Comput. Digital Tech.,2008

5. Hybrid BIST scheme for multiple heterogeneous embedded memories;Denq;IEEE Des. Test Comput.,2009

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3. Frei-Chen bases based lossy digital image compression technique;Applied Computing and Informatics;2020-07-29

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