Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs-Reference-Cited by-同舟云学术

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Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs

Published:2007-04 Issue:4 Volume:56 Page:545-556
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Ruan Xiaoyu,Katti Rajendra S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/4118665/04118676.pdf?arnumber=4118676

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic;Journal of Electronic Testing;2020-06

2. Divide and compress discrete cosine lossless compression coder to reduce dimensionality of test data;Journal of Ambient Intelligence and Humanized Computing;2020-05-30

3. Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests;ACM Transactions on Design Automation of Electronic Systems;2016-12-28

4. Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-02

5. Binary Difference Based Test Data Compression for NoC Based SoCs;2012 IEEE Computer Society Annual Symposium on VLSI;2012-08

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