An analytical model of thermal mechanical stress induced by through silicon via
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy
Link
https://iopscience.iop.org/article/10.1088/1674-1056/24/5/056601/pdf
Reference23 articles.
1. TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
2. Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling
3. Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
4. Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
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1. Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array;Micromachines;2023-07-25
2. The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System;Symmetry;2023-02-04
3. Thermal-Stress Coupling Optimization for Coaxial through Silicon Via;Symmetry;2023-01-17
4. Power and Thermal Constraints-Driven Modeling and Optimization for Through Silicon Via-Based Power Distribution Network;Journal of Electronic Packaging;2018-08-03
5. Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits;Chinese Physics B;2016-11
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