Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs-Reference-Cited by-同舟云学术

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Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Published:2012-01 Issue:1 Volume:20 Page:186-191
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Wu Xiaoxia,Zhao Wei,Nakamoto Mark,Nimmagadda Chandra,Lisk Durodami,Gu Sam,Radojcic Riko,Nowak Matt,Xie Yuan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6099858/05658180.pdf?arnumber=5658180

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Benchmarking Frequency-Dependent Parasitics of Fine-Pitch Off-Chip I/Os for 2.5D and 3D Heterogeneous Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-12

3. A High Static Performance Hierarchical Three-Dimensional Shifted Completely Connected Network;IEEE Access;2022

4. 3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations;IEEE Transactions on Emerging Topics in Computing;2021-04-01

5. Your hardware is all wired up!;Proceedings of the 12th International Workshop on Network on Chip Architectures;2019-10-13

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