Affiliation:
1. School of Microelectronics, Xidian University, Xi’an 710071, China
Abstract
In this paper, a thermal-stress coupling optimization strategy for coaxial through silicon via (TSV) is developed based on the finite element method (FEM), artificial neural network (ANN) model and particle swarm optimization (PSO) algorithm. In order to analyze the effect of design parameters on the thermal-stress distribution of coaxial TSV, the FEM simulations of coaxial TSV are conducted by COMSOL Multiphysics. The structure of coaxial TSV is symmetric. The mapping relationships between the design parameters and performance indexes are described by ANN models based on the simulation data of FEM. In addition, the multi-objective optimization function is formulated based on the desired performance indexes, and then the design parameters are optimized by the modified PSO algorithm. Based on the optimized design parameters, the effectiveness of the developed method is validated by FEM simulations. The simulated performance indexes agree well with the desired ones, which implies that the design parameters of coaxial TSV can be optimized to control the thermal-stress distribution. Therefore, the thermal-stress coupling optimization of coaxial TSV can achieve thermal-stress management to improve its reliability.
Funder
Youth Talent Fund of the Joint Fund of the Ministry of Education for Equipment Pre-Research
Wuhu and Xidian University special fund for industry-university-research cooperation
Cooperation Program of XDU-Chongqing IC Innovation Research Institute
Fundamental Research Funds for the Central Universities
Innovation Fund of Xidian University
Subject
Physics and Astronomy (miscellaneous),General Mathematics,Chemistry (miscellaneous),Computer Science (miscellaneous)
Reference32 articles.
1. A wafer-scale 3-D circuit integration technology;Burns;IEEE Trans. Electron Dev.,2006
2. Wang, X., Yang, Y., Chen, D., and Li, D. (2022, October 11). A High-Efficiency Design Method of TSV Array for Thermal Management of 3D Integrated System. Available online: https://ieeexplore.ieee.org/document/9915793.
3. 3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias;Knickerbocker;IEEE J. Solid-State Circ.,2006
4. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip;Shulaker;Nature,2017
5. Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design;Xu;IEEE Electr. Device Lett.,2012
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献