A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture-Reference-Cited by-同舟云学术

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Yue Jinshan¹,He Chaojie¹,Wang Zi¹,Cong Zhaori¹,He Yifan²,Zhou Mufeng²,Sun Wenyu²,Li Xueqing²,Dou Chunmeng¹,Zhang Feng¹,Yang Huazhong²,Liu Yongpan²,Liu Ming¹

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China

2. Tsinqhua University,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067779.pdf?arnumber=10067779

Reference6 articles.

1. A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

2. DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC;ueyoshi;ISSCC,2022

3. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

4. A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

5. A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

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