A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS-Reference-Cited by-同舟云学术

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Park Jung-Hun¹,Lee Hyeonseok¹,Cho Hoyeon¹,Lee Sanghee¹,Lee Kwang-Hoon¹,Ko Han-Gon²,Jeong Deog-Kyoon¹

Affiliation:

1. Seoul National University,Seoul,Korea

2. ONEsemiconductor,Gyeonggi,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067552.pdf?arnumber=10067552

Reference5 articles.

1. 22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique

2. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

3. A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

4. A 20 Gb/s/pin 1.18pJ/b 1149µm2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS;moon;ISSCC,2022

5. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

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1. A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

2. An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024

3. A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05