A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus-Reference-Cited by-同舟云学术

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Lee Daewoong¹,Kwon Hye-Jung¹,Kwon Daehyun¹,Baek Jaehyeok¹,Cho Chulhee¹,Kim Sanghoon¹,An Donggun¹,Chang Chulsoon¹,Lim Unhak¹,Im Jiyeon¹,Sung Wonju¹,Kim Hye-Ran¹,Park Sun-Young¹,Kim HyoungJoo¹,Seol Hoseok¹,Kim Juhwan¹,Shin Junabum¹,Kang Kil-Youna¹,Kim Yona-Hun¹,Kim Sooyoung¹,Park Wansoo¹,Kim Seok-Jung¹,Lee Chanyong¹,Lee Seungseob¹,Park TaeHoon¹,Oh ChiSung¹,Ban Hyodong¹,Ko Hyungjong¹,Song Hoyoung¹,Oh Tae-Young¹,Hwang SangJoon¹,Oh Kyung Suk¹,Choi JungHwan¹,Lee Jooyoung¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731614.pdf?arnumber=9731614

Reference7 articles.

1. A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and 10 Circuitry for Low-Noise Operation;kim;ISSCC,2021

2. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

3. 22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

4. 25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling

5. 3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

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