13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration-Reference-Cited by-同舟云学术

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13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration

Published:2024-02-18 Issue: Volume: Page:242-244
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Cho Sung-Yong¹,Choi Moon-Chul¹,Baek Jaehyeok¹,An Donggun¹,Kim Sanghoon¹,Lee Daewoong¹,Yang Seongyeal¹,Kang Gil-Young¹,Park Juseop¹,Lee Kyungho¹,Jung Hwan-Chul¹,Cho Gunhee¹,Lee Chanyong¹,Kim Hye-Ran¹,Shin Yong-Jae¹,Park Hanna¹,Lee Sangyong¹,Kim Jonghyuk¹,Won Bokyeon¹,Mok Jungil¹,Kim Kijin¹,Lim Unhak¹,Jin Hong-Jun¹,Lee YoungSeok¹,Kim Young-Tae¹,Ha Heonjoo¹,Ahn Jinchan¹,Sung Wonju¹,Jang Yoontaek¹,Song Hoyoung¹,Ban Hyodong¹,Park TaeHoon¹,Oh Tae-Young¹,Yoo Changsik¹,Hwang SangJoon¹

Affiliation:

1. Samsung Electronics,Hwasung,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454354.pdf?arnumber=10454354

Reference4 articles.

1. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

2. 25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling

3. A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

4. 23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface

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