A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces
Author:
Affiliation:
1. Department of Electrical Engineering, Korea University, Seoul, South Korea
2. SK Hynix Inc., Icheon, South Korea
3. Department of Semiconductor System Engineering, Korea University, Seoul, South Korea
Funder
National Research Foundation of Korea
Korean Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10192489/10061853.pdf?arnumber=10061853
Reference26 articles.
1. A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface
2. A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer
3. A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory Interfaces
4. A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations
5. 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
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