A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations
Author:
Funder
Samsung Electronics Company Ltd
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9694622/09501157.pdf?arnumber=9501157
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations;2023 20th International SoC Design Conference (ISOCC);2023-10-25
2. A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-08
3. PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
4. A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19
5. Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-08
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