A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications
Author:
Affiliation:
1. Korea University,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067541.pdf?arnumber=10067541
Reference7 articles.
1. A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations
2. A 52-Gb/s Sub-1 pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects;wang;IEEE Symp VLSI Circuits,2019
3. A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier;yoo;ISSCC,2020
4. A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler
5. Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler;2023 20th International SoC Design Conference (ISOCC);2023-10-25
2. A Bang-Bang Phase Detector for PAM-N Signaling;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
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