A Bang-Bang Phase Detector for PAM-N Signaling
Author:
Affiliation:
1. The Hong Kong University of Science and Technology,Optical Wireless Lab, Integrated Circuits Design Center,Dept. of ECE,Hong Kong SAR,China
2. Sharif University of Technology,Department of Electrical Engineering,Tehran,Iran
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396104.pdf?arnumber=10396104
Reference10 articles.
1. A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS
2. Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links
3. Challenges in the design high-speed clock and data recovery circuits
4. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
5. A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance
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