A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA
2. Department of Electrical and Computer Engineering, University of California at Los Angeles (UCLA), Los Angeles, CA, USA
Funder
Realtek Semiconductor Corporation
Taiwan Semiconductor Manufacturing Company (TSMC) University Shuttle Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9866858/09732686.pdf?arnumber=9732686
Reference22 articles.
1. A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
2. Channel-adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver;hossain;IEEE J Solid-State Circuits,2018
3. A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
4. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS
5. A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects
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1. A Bang-Bang Phase Detector for PAM-N Signaling;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O;2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2022-10-28
3. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector;2022 IEEE Nordic Circuits and Systems Conference (NorCAS);2022-10-25
4. Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver;IEICE Electronics Express;2022-08-10
5. Low Jitter Design for Quarter-rate CDR of 100Gb/s PAM4 Optical Receiver;IEICE ELECTRON EXPR;2022
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