A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface
Author:
Funder
National Key Research and Development Program of China
National Natural Science Foundation of China
Publisher
Elsevier BV
Reference26 articles.
1. Universal chiplet interconnect express (UCIe): An open industry standard for innovations with chiplets at package level;Das Sharma;IEEE Trans. Compon, Packag. Manuf. Technol.,2022
2. A 0.90-Tb/s/in 1.29-pJ/b wireline transceiver with single-ended crosstalk cancellation coding scheme for high-density interconnects;Liu;IEEE J. Solid-State Circuits,2023
3. A 4nm 32Gb/s 8Tb/s/mm die-to-die Chiplet using NRZ single-ended transceiver with equalization schemes and training techniques;Seong,2023
4. A 0.85-pJ/b 16-Gb/s/pin single-ended transmitter with integrated voltage modulation for low-power memory interfaces;Jeong;IEEE J. Solid-State Circuits,2023
5. A 20-Gb/s/pin compact single-ended DCC-less DECS transceiver with CDR-less RX front-end for on-chip links;Seo;IEEE J. Solid-State Circuits,2023
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