Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part II: PBTI Aging and Optimization-Reference-Cited by-同舟云学术

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Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part II: PBTI Aging and Optimization

Published:2024-08 Issue:8 Volume:71 Page:4469-4475
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Liu Yong¹,Wang Da¹^ORCID,Ren Pengpeng¹^ORCID,Li Jie¹^ORCID,Qiao Zheng¹^ORCID,Wu Maokun¹,Wen Yichen¹,Zhou Longda¹^ORCID,Sun Zixuan²^ORCID,Wang Zirui²,Han Qinghua³,Wu Blacksmith³,Cao Kanyu³,Wang Runsheng²^ORCID,Ji Zhigang⁴^ORCID,Huang Ru²

Affiliation:

1. National Key Laboratory of Advanced Micro and Nano Manufacture Technology, Shanghai Jiao Tong University, Shanghai, China

2. Institute of Microelectronics, Peking University, Beijing, China

3. ChangXin Memory Technologies, Hefei, China

4. Beijing Superstring Academy of Memory Technology, Beijing, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/16/10609410/10555029.pdf?arnumber=10555029

Reference22 articles.

1. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

2. DRAM reliability overview;Park

3. Enhanced DRAM Single Bit Characteristics from Process Control of Chlorine

4. Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era

5. 6F2 buried wordline DRAM cell for 40 nm and beyond;Schloesser

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