A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces
Author:
Affiliation:
1. Department of Semiconductor System Engineering, Korea University, Seoul, South Korea
2. Department of Electrical Engineering, Korea University, Seoul, South Korea
Funder
Institute of Information and communications Technology Planning and Evaluation (IITP) Grant
Korea Government (MIST)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/8920/10581876/10423297.pdf?arnumber=10423297
Reference14 articles.
1. Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane
2. 23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme
3. 25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation
4. 28.5 A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces
5. A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
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