25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation-Reference-Cited by-同舟云学术

25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Kim Kyunghoon,Chae Joo-Hyung,Yang Jaehyeok,Kang Jihyo,Lee Gangsik,Byeon Sangyeon,Kim Youngtaek,Kim Boram,Kim Dong-Hyun,Cho Yeongmuk,Choi Kangmoo,Park Hyeongyeol,Ji Junghwan,Jeong Sera,Joo Yongsuk,Cha Jaehoon,Park Minsoo,Kim Hongdeuk,Park Sijun,Kong Kyubong,Kim Sunho,Lee Sangkwon,Chun Junhyun,Kim Hyungsoo,Cha Seonyong

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365844.pdf?arnumber=9365844

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