13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets-Reference-Cited by-同舟云学术

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13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

Published:2024-02-18 Issue: Volume: Page:250-252
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Seong Kihwan¹,Oh Wooseuk¹,Lee Hyunwoo¹,Bae Gyeomje¹,Suh Youngseob¹,Lee Hyemun¹,Kim Juyoung¹,Kim Eunsu¹,Kang Yeongeon¹,Mo Gunhu¹,Lee Youjin¹,Kim Mingyeong¹,Lee Seongno¹,Park Donguk¹,Yoo Byoung-Joo¹,Rhew Hyo-Gyuem¹,Shin Jongshin¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454481.pdf?arnumber=10454481

Reference7 articles.

1. A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection

2. A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

3. A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET

4. 11.3 A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications

5. A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS

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