A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS-Reference-Cited by-同舟云学术

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Gangasani G.¹,Hanson D.¹,Storaska D.¹,Xu H. H.¹,Kelly M.¹,Shannon M.¹,Sorna M.¹,Wielgos M.¹,Ramakrishna P. B.²,Shi S.³,Parker S.¹,Shukla U. K.²,Kelly W.¹,Su W.³,Yu Z.⁴

Affiliation:

1. Marvell,NY

2. Marvell,Bangalore,India

3. Marvell,Shanghai,China

4. Marvell,Santa Clara,CA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731636.pdf?arnumber=9731636

Reference3 articles.

1. 11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology

2. 11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS

3. 6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS

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