An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation
Author:
Affiliation:
1. Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA
2. Mediatek, Irvine, CA, USA
Funder
Center for Design of Analog-Digital Integrated Circuits
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/4/10608476/10436129.pdf?arnumber=10436129
Reference43 articles.
1. 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
2. A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
3. A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
4. A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS
5. 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
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