A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update-Reference-Cited by-同舟云学术

A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update

Published:2023-02-19 Issue: Volume: Page:
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Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Mori Haruki¹,Zhao Wei-Chang¹,Lee Cheng-En¹,Lee Chia-Fu¹,Hsu Yu-Hao¹,Chuang Chao-Kai¹,Hashizume Takeshi²,Tung Hao-Chun¹,Liu Yao-Yi¹,Wu Shin-Rung¹,Akarvardar Kerem³,Chou Tan-Li¹,Fujiwara Hidehiro¹,Wang Yih¹,Chih Yu-Der¹,Chen Yen-Huei¹,Liao Hung-Jen¹,Chang Tsung-Yung Jonathan¹

Affiliation:

1. TSMC,Hsinchu,Taiwan

2. TSMC,Yokohama,Japan

3. TSMC,San Jose,CA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067555.pdf?arnumber=10067555

Reference4 articles.

1. A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

2. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

3. A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference

4. PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

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