A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference-Reference-Cited by-同舟云学术

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A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference

Published:2022-06-12 Issue: Volume: Page:
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Container-title:2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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Author:

Wang Hechen¹,Liu Renzhi¹,Dorrance Richard¹,Dasalukunte Deepak¹,Liu Xiaosen¹,Lake Dan¹,Carlton Brent¹,Wu May¹

Affiliation:

1. Intel Corporation,Intel Labs,Hillsboro,OR,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9830116/9830138/09830322.pdf?arnumber=9830322

Reference9 articles.

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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