Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC
Author:
Affiliation:
1. Chung-Ang university, Seoul, Dong-jak Gu, Republic of Korea
2. Chung-Ang university, Seoul, Republic of Korea
3. Chunag-Ang university, Seoul, Dong-jak Gu, Republic of Korea
Funder
National Research Foundation of Korea
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3665314.3670819
Reference10 articles.
1. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks
2. S. Sharma, W.-C. Wang, C. DeLude, M. Lee, N. M. Rahman, N. V. Kidambi, J. Romberg, and S. Mukhopadhyay, "Afe-cim: A current-domain compute-in-memory macro for analog-to-feature extraction," in ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, pp. 33--36.
3. A. Kneip M. Lefebvre J. Verecken and D. Bol "A 1-to-4b 16.8-pops/w 473-tops/mm2 6t-based in-memory computing sram in 22nm fd-soi with multi-bit analog batch-normalization " in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) 2022 pp. 157--160.
4. C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism
5. H. Wang R. Liu R. Dorrance D. Dasalukunte X. Liu D. Lake B. Carlton and M. Wu "A 32.2 tops/w sram compute-in-memory macro employing a linear 8-bit c-2c ladder for charge domain computation in 22nm for edge inference " in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2022 pp. 36--37.
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