A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS-Reference-Cited by-同舟云学术

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS

Published:2023-04 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Zhang Shiwei¹,Deng Wei¹,Jia Haikun¹,Liu Hongzhuo¹,Sun Shiyan¹,Guan Pingda¹,Chi Baoyong¹

Affiliation:

1. Tsinghua University,Beijing,China

Funder

Samsung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121218.pdf?arnumber=10121218

Reference6 articles.

1. Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM

2. A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise

3. Analysis and Design of a 54 GHz Distributed “Hybrid” Wave Oscillator Array With Quadrature Outputs

4. On the Remarkable Performance of the SeriesResonance CMOS Oscillator;pepe;IEEE TCAS-I,2018

5. Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise

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