A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM-Reference-Cited by-同舟云学术

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A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM

Published:2023-11-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Asian Solid-State Circuits Conference (A-SSCC)
language:
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Author:

Li Yixi¹,Zhang Zhao¹,Chen Yong²,Shen Xinyu¹,Zhang Zhaoyu¹,Qi Nan¹,Liu Jian¹,Wu Nanjian¹,Liu Liyuan¹

Affiliation:

1. Institute of Semiconductors,Chinese Academy of Sciences,China

2. University of Macau,Macau,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347557/10347908/10347983.pdf?arnumber=10347983

Reference11 articles.

1. A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

2. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

3. A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM

4. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

5. A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of -256 dB

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Multireference PLL: Theory and Implementation;IEEE Journal of Solid-State Circuits;2024-07

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