A Sub-50-fs<sub>rms</sub> Jitter Fractional-<i>N</i> CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm-Reference-Cited by-同舟云学术

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A Sub-50-fs_rms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

Published:2024-03 Issue:3 Volume:59 Page:677-689
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ye Zonglin¹^ORCID,Geng Xinlin¹^ORCID,Xiao Yao¹^ORCID,Xie Qian¹^ORCID,Wang Zheng¹^ORCID

Affiliation:

1. School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10445390/10402556.pdf?arnumber=10402556

Reference32 articles.

1. A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

2. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

4. A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

5. An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

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