A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation-Reference-Cited by-同舟云学术

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A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Published:2016-12 Issue:12 Volume:51 Page:3078-3092
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Markulic Nereo,Raczkowski Kuba,Martens Ewout,Paro Filho Pedro Emiliano,Hershberg Benjamin,Wambacq Piet,Craninckx Jan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7756673/07583711.pdf?arnumber=7583711

Cited by 54 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD;IEEE Journal of Solid-State Circuits;2024-08

2. A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

3. A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs;Microelectronics Journal;2024-04

4. A Sub-50-fs_rms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm;IEEE Journal of Solid-State Circuits;2024-03

5. Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop;IEEE Journal of Solid-State Circuits;2024

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