A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}

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A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$

Published:2024-04-21 Issue: Volume: Page:1-2
ISSN:
Container-title:2024 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Ye Zonglin¹,Geng Xinlin¹,Shi Zhixiang¹,Zhang Hongyang¹,Xie Qian¹,Wang Zheng¹

Affiliation:

1. University of Electronic Science and Technology of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10528947/10528954/10529020.pdf?arnumber=10529020

Reference4 articles.

1. A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

2. A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1 fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels;Geng;IEEE CICC,2023

3. A -58dBc-Worst-Fractional-Spur and -234dB-FoM 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator Generating a Nonlinearity-Robust DTC-Control Word;Seong;IEEE ISSCC,2020

4. 4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

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